1. Field of the Invention
The present invention relates to a CMOS semiconductor device having a lightly doped drain (LDD) NMOS transistor and a single drain type PMOS transistor, and the methods for constructing the same.
2. Description of Related Art
The development of a fast MOS device has been usually accompanied by its miniaturization. With greater packing density of transistors, the field strength inside such devices also has increased. This causes several problems, such as a decrease in threshold voltage, punch-through, and "hot-carrier" effect. These problems degrade device characteristics.
Among all of the above problems, the hot carrier effect is especially detrimental to MOS device performance. The hot carrier effect is caused by an acceleration of a carrier inside a channel due to an intense field that is present across the depletion layer near the drain. A carrier which has gained sufficient energy may penetrate through the potential barrier between the silicon and the gate oxide film, entering the gate oxide film as a "hot carrier." The hot-carrier inside the oxide film may then become trapped and change the shape of the potential barrier at the interface between the silicon and the oxide film, consequently altering the threshold voltage and/or the mutual conductance.
An accelerated carrier inside the channel may generate new electron/hole pairs via an impact ionization. The newly generated carriers, in turn, may produce other electron/hole pairs via the same process. Thus, the impact ionization may propagate throughout the channel and produce an avalanche of hot carriers to be injected to the gate oxide film.
In addition, holes generated by the ionization increase the potential of the substrate by forming currents. The increase in the substrate potential may cause a break-down of parasitic bipolar transistors, and change the drain withstanding voltage.
The hot-carrier effect is more pronounced in NMOS transistors than in PMOS transistors, because a channel electron in NMOS can cause an impact ionization more readily than a channel hole in PMOS. In addition, the NMOS channel electron can move more easily into the NMOS oxide film than the PMOS channel hole into the PMOS oxide film. This is because the potential barrier between the silicon and the gate oxide film in NMOS is lower than that in PMOS.
Conventionally, LDD NMOS transistors have been used to relieve the hot-carrier effect. In an LDD NMOS transistor, lowering the impurity concentration near the drain reduces the field intensity and diminishes the hot-carrier effect. However, the low impurity concentration of the drain region adds a parasitic resistance between the drain and the channel. The parasitic resistance decreases the drain current.
If the impurity concentration near the drain region becomes too large, the substrate current also becomes large, amplifying the hot carrier effect. On the other hand, if the impurity concentration becomes too low, the drive current decreases because of a parasitic resistance. Thus, the impurity concentration is usually carefully selected to take account of both the hot carrier effect and the parasitic resistance.
One conventional CMOS design which addresses the above problems comprises the LDD NMOS transistors and the PMOS transistors of the single-drain type. In the design, the gate side wall spacers of NMOS and PMOS transistors are usually set to an equal thickness to simplify their manufacture.
n.sup.+ source and drain regions of the LDD NMOS transistors are generally formed by As ion-implantation, because the diffusion rate of As is low and allows the formation a thin junction. On the other hand, the p.sup.+ source and drain regions of PMOS transistors are generally formed by B ion-implantation.
Because B diffuses faster than As, the connection depth and side spreading of p.sup.+ source and drain regions are larger than those of n.sup.+ regions. Consequently, the effective channel length of the PMOS transistor is much shorter than that of the NMOS transistor. This implies that, if the size of NMOS channels were reduced, then the size of PMOS channels would be reduced even further. Such undesired reduction in PMOS channel size results in the distortion of PMOS structures. Thus, it is difficult to use the conventional technique to produce CMOS devices with very small LDD NMOS transistors.